Registered on :
07-12-2004
From Italy
Messages : 182
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The attached STVD 4.0 project shows a bug of the ST7FOXA0 simulator.
According to the stimuli file "Bug.in", after 64000 clock cycles there are an input capture and a timebase event.
The corresponding interrupt handlers are correctly prioritized as reported in the datasheet: first the input capture one, then the timebase one.
The simulator bug deals with the missing LTCSR_TBF clearing that the hardware does after a read to LTCSR, which is exactly the intended side effect of the instruction:
BTJF LTCSR,#LTCSR_TBF,IC_End
Since IC_ISR clears LTCSR_TBF LTCSR_TBF while the timebase interrupt request is waiting to be serviced, TB_ISR should not be executed but this does not happen.
Regards
EtaPhi
| Attachments : |  TbIcBug.zip | | | |
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ST7FOXA0 simulator bug
Posted 07-07-2008 at 08:33 
